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[Àü°øµµ¼/´ëÇб³Àç] Çѱ¹¾îÆÇ VERILOG HDL µðÁöÅÐ ¼³°è¿Í ÇÕ¼ºÀÇ ±æÀâÀÌ
Verilog HDL : a guide to digital design and synthesis
SAMIR PALNITKAR Àú/ÀåÈÆ ¿ªIµµ¼ÃâÆÇ È«¸ª(È«¸ª°úÇÐÃâÆÇ»ç)I2005.09.10
30,000¿ø
900P (3%)
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